RCD - Rotating Clock Divider



RCD - Rotating Clock Divider

This is an Audulus port of the 4ms RCD Eurorack module. It features eight divided outputs with various divisions of the input clock. The maximum divisor can be set at 8, 16, 32 or 64. The divisor attached to each output can be rotated. There is a standard mode where each output is one higher than the previous one and a spread mode where the outputs are spread across the divisor range. When spread mode is on and the max divisor is set to 8, the divisors switch to 1, 2, 3, 4, 6, 8,12, and 16 which provides traditional timing intervals. The count can be synced to the downbeat or upbeat. There is an auto reset which provides for periodic resets of the counts. See the 4ms RCD documentation at: https://4mscompany.com/clocker/manual/RCD-manual-1.2.pdf for details. Note that this module only implements trigger mode. Gate mode (50% duty cycle) is not currently available.


Input Signal Range Notes
clock 0-1 clock signal output clocks have the same pulse width as the input
reset 0-1 gate resets all counters

Output Signal Range Notes
divclock 0-1 clock signal divided output clocks
autoreset 0-1 clock signal auto reset - connect to rs input for autoreset (see docs)


Control Function Notes
rotate%20clock rotates the divisor for each output see docs
max%20div sets the maximum divisor to 8, 16, 32, or 64 see docs
beat sets the count on the downbeat or upbeat blue is downbeat (see docs)
spread sets spread mode red is spread mode (see docs)


Meter Displays Notes
divide%20by current divisor for each output
max%20disp maximum divisor

Version History

Revision File Date Notes
1.1 RCD V1.1.audulus (199.8 KB) 07/20/2018 improved efficiency
1.0 superceded 07/20/2018 initial upload


Revision File Date Notes
1.1 RCD demo V1.1.audulus (845.9 KB) 07/20/2018 initial upload

uRCD Single Channel Rotating Clock Divider

I came across the RCD while researching the 4ms PEG and thought it would make a neat Audulus module. This model should be pretty close to the original running in trigger mode with the optional extender. Version 1 is a bit more CPU intensive than I would like, but the flexibility of the original resulted in quite a few expression statements. I’m still working on trying to improve the efficiency. Gate mode ( outputs are 50% duty cycle square waves) is computationally difficult for divisors that are not multiples of 2 so I elected to omit it to save some CPU cycles.


I love it :wink: I think this will probably blow @biminiroad’s mind when he gats a chance to check it out.

The internal structure is pretty impressive as well.

I made a little gate utility to convert any clock signal to a 50% duty cycle.

It’s not an integrated solution, so it takes a cycle to figure out the frequency, but it works well enough for when you need a gate instead of a trig. I suppose you could use the gate smear utility as well, but this approach doesn’t require adjustment when you are rotating away.


I had come up with a similar solution, but adding one and switch to every output would have increased the CPU load significantly. Using it externally as in your example only adds the load when it’s necessary. It would be really nice to have a true switch which could disconnect a patch segment so that the code wouldn’t execute. That way you could arrange it so that only the parts of the patch in use actually ran.


That and a normalization option for inputs. Maybe in Audulus 4.


I’m curious as to why you added the timer and expression rather than simply using the output of the phasor.


So it will turn off when you stop the clock, it’s a pet peev that sometimes I turn off the master clock and part of the patch will still be running. The zerocross node only updates the rate when a new pulse is receives, so the timer is there to ensure that the signal cuts out shortly after the duty cycle goes low.

edit: I guess thinking about it now, that kind of makes the phasor irrelevant, huh?

edit2: It also takes off some cpu to avoid the phasor so here is the revised version.

50 percent duty cycle V2.audulus (215.8 KB)