I’m trying to recreate a D-Latch, the building block of a Shift Register, without using the S&H node. I applied the exact logic diagram from wikipedia, and yes I’ve tested the truth tables of my logic gates. I think it’s working as intended, but the crucial difference between my FF and the “Fast FF” of uTuring seems to be that, in ‘Fast FF’ the data is released on clock down, and on mine it happens on clock up. I could probably find a cheat around that, but more fundamentally I wonder why a (seemingly) logically rigorous D-Latch doesn’t correctly behave in a shift register.
This is what my FF/D-Latch looks like:
Sorry for using Audulus for logic and math instead of music. It’s just too interesting