Build Request: Clock Multiplier

There is an issue I run into from time to time. If I send a clock through a multiplier module, when I stop the clock the multiplier keeps outputting a pulse. Is there a way to have it not do this? The use case is when you are just using a simple clock and adding some faster gates with one of these.

Multiplier issue.audulus (15.7 KB)

Also, I have found that if there is any slight clock variability from an external clock coming into Audulus, it messes up the delay modules significantly. Is there a way to resolve that?

It seems like the Delay Tempo Sync needs a perfect signal…

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Clock multipliers are a bit of an issue in Audulus. It’s simple to divide a clock using a counter, but in order to generate a faster clock than the input, you need to use an oscillator running at the higher rate. The multiplier uses a zero crossing detector to calculate the incoming frequency to control a phasor node and a sync pulse to help keep the clocks in sync. This approach works OK with a stable input clock but doesn’t do well if the input clock has any variability. You are always better off using a faster clock and dividing it down. As far as stopping the clock the easiest way is probably to use a crossfade to shut it off at the same time as the input.I haven’t really played with the tempo sync so I don’t have an answer but if the delay time varies even a little you’ll likely have problems.