Help "taming" external gate/clock signal?

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1

Using Audulus with an ES-8. I love it!
Unfortunately I am running into a problem with a signal coming from my Animodule TikTok clock div/mult.
With my outboard modules, I can use the longer division signals as Gates, but when I throw one into Audulus (via ES-8) I get double triggering – one at the start of the gate, one at the end.
Here is an image to illustrate the issue:

IMG_2B05580B0BFA-1
IMG_2B05580B0BFA-12048×1536 234 KB

This is the gate waveform straight from TikTok into ES-8 & Audulus via ADC node.

I get retriggering on Envelope modules and they usually won’t hold the gate high.

Again, this is not an issue with my external hardware modules – they accept this wave as a Gate.

So how can I “tame” this signal to act like a normal Gate inside Audulus?

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2

You run the signal through a “x>.01” expression node like so

clock%20clean%20up

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3

I tried this expression and it definitely helped, but I am still getting spikes:

image
image2048×1536 355 KB

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4

Attach a knob to an expression node with x>(knob*0.1) and use the knob to tune it until that doesnt happen anymore. Basically you’re still “ringing” past that threshold and it needs to be increased.

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5

The threshold knob seems to have worked.
Thank you so much!
Making it into a submodule now :slightly_smiling_face:

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6

That’s a good practice :ok_hand:

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