I was thinking about making an Audulus emulation of the woggle bug but I need to better emulate the PLL circuit that it implements.
The PLL in question is an XOR circuit with the output running through an extreme LPF that converts it into a DC offset that. That DC offset is used for the pitch CV of the VCO that alse feeds back into the XOR logic input.
http://wiard.com/support/manuals/WoggleBug-031001.pdf
Just stacking reference info
I had a shot at building a PLL a while back without much success. The best design I came up with used a zero crossing node and the sync input on a phasor.
That was how I made the garbler fx module! but I actually had some luck replicating the described behavior of an XOR based PLL at low frequencies. So I think now it’s finding the proper way to scale it up to audio frequencies.
ring mod PLL test.audulus (29.6 KB)
It does a pretty good job of maintaining a 90 degree phase angle with full bipolar square wave inputs.
It even gets stuck on harmonics, like the analog version. 
last update for today, here is the most simplified version of the previous example. Tomorrow I will try to figure out how to calculate the appropriate LPF alpfa value and test a few methods of frequency tracking for the internal VCO.
Simplified PLL.audulus (7.1 KB)
Let me know if you have any success, a working PLL could be useful.
I kind of hacked the pitch tracking with the exponentiator expression using the zero crossing value of the reference signal as the multiplier for 2^o. All this is to say that the pitch tracking is more or less automatic and the feedback loop is just there to make it squonky.
prototype pll.audulus (154.9 KB)
It may not be perfect, but I think it should be a good starting point to try and build a wogglebug around.
This is such an interesting (and completely over my head) concept! I wish I had the knowledge/experience to figure out how to model things like this 
I haven’t given up on the PLL although so far I haven’t had much luck. I found the following reference which might be useful:
https://www.analog.com/en/analog-dialogue/articles/phase-locked-loop-pll-fundamentals.html#
It describes the PLL circuit used in the ADF4xxx family of ICs which I believe is similar to the CD4046 IC used in the Wogglebug
After spending the morning attempting to model the circuit described in the reference above, I’m becoming increasingly convinced that it’s not workable in Audulus. There are some other alternatives which are still probably worth exploring but so far the D flip-flop phase detector has not really behaved as you would expect. I’m not sure why but feedback circuits are always tricky to model.
I gotta know what your phase comparator expression was. 
edit: I looked at the diagram in the linked reference and saw this diagram
And realized it was a two input flip flop, making an expression kind of irrelevant. 
But it did inspire me to try using a flip flop instead of a simple ring mod, and I kind of got it to work! It does seem to get stuck on harmonics unless you mess with the loop filter cutoff, but when it works it’s always a 180 degree phase difference. That’s the exact opposite of the diagram, but I still think it’s pretty neat!
Note, I do not think this patch will scale to audio rates because in order to mix the two gate inputs I used a timer node.
Controlled-Root Formulation For DPLLs - S. Stephens and J. Thomas - JPL 1995.pdf (1.4 MB)
A friend of mine passed along this PDF on digital PLLs but I must confess the math was too much for me to track. I’ll leave it here in case anyone might find it useful.
I tried to model the flip-flop based phase comparator. In this case the two D-type flip flops are used as latches. The data input is held at 1 and the trigger is fed to the clock input. You have to be careful because D-type flip-flops are active low not high so the flip-flop is reset when the reset line goes low and is clocked on the falling edge of the clock pulse. The article did not specify a value for the delay but if I undertand the circuit, it would have to be very short. In any case, I got some very strange output from the delay line. I was feeding it ones and zeros but getting other values out, at least according to the waveform node. There is a quadrature multiplier that is also used as a phase detector but I haven’t found a good description as yet.
I know the math has to be some next level concept if you (as one of the main people I look to for help with understanding DSP math) feel that the math involved is a little too intense! Holy hieroglyphics, Batman! 
