In search of a consistent reset input
  • I realized that I have pretty much stopped using the reset inputs on Audulus sequencers because they work inconsistently. The main problem is that the reset message needs to be sent when the gate input is low, meaning it doesn't always reset. I would propose adding a timer node and an expression to the module in order to force the reset whenever the message is received to create consistent intuitive results when patching around the reset feature.

    Also, didn't there use to be a sequencer category in the help section?
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  • Recently I’ve tried to design my resets so that if reset is held high during one clock (gate) cycle you get a reset. I’ve found that trying to arrange it so that you can get a reset while the gate is held high often requires adding pulse circuits that seem to cause as many problems as they solve. The timer is an approach I haven’t tried so it’s certainly worth keeping in mind.
  • Yes, this one has been straining my brain. Have been trying to figure this out for my own sequencer. Thanks for sharing!
  • Having no problems with it. I sometimes use this little guy. I'ts based on the classic Count^. The first cycle starts always at 0 - and if you wish you can start the other cycles at 1.

    I've also added basic Signal processing for you: Basic Signal Processing
    So you can choose, which signals are dominant, when they occur at the same time.
    Just look at my stuff.
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  • @Experiment1 Thanks for the examples, I enjoy your sequencer designs so I'm glad you are a part of the conversation. The thing about the reset method you employ is that it will sometimes hold on a step rather than reset. I'm not sure why, as you clearly have the fundamental logic there, but I have revised your patch to show you what I am talking about.

    @RileyGuy I'm right there with you, that's why for so long I just gave up on reliable resets.

    @stschoen That is very interesting, I will have to go back and take a closer look at your counter module :)
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  • Hey @RobertSyrett, you're right, I can clearly see what you're describing! The problem is the Sample & Hold: It only revises its value on the rising edge - so I've put a positive edge before it and it works as your default design now. I usually convert a gate signal to an edge signal, when I use it as a clock... that's maybe the reason why it did not occur to me.
    I really don't like to work with timer in sequencers, because everything should have a clear state at anytime, right? ...BUT I'm quite sure that I've used timers somewhere before to solve the problem with the priority of signals. :P

    I would use the SR-flipflops like in this picture:
    image


    Set it somewhere right after the the clock input so that the clock signal won't go through as long as reset is high (oh and reset should also reset your internal S&H memory).
    That way you can prioritize signals ...or make a nice burst generator. ;P
    Did somebody made something like a One Shot rhythm generator? A module like Variatic Erumption from Noise Engineering?
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  • Very nice. Even though I'm using a timer, it's really being used as a gate interrupt on the input to the S&H (almost the inverse of how you are using the delta node actually) and will only cause a glitch if you are running the counter at audio rates. So don't use the timer method as a sync function your wavetable oscillator.

    There should definitely be more burst generators in Audulus (~-_-)~

    Also, I was looking at your design, it would be possible to jump to any value with your design, no? Just switch out 1 with a variable that can be clamped between 0 and max. Could be useful for all sorts of creative sequencer designs.
  • I'll look at it tomorrow. I'd say you have to edit the term
    (r==1)*(Signal==Max)*(1-reset)?1:x

    I've found that my design without the timer isn't quite stable enough, sometimes on high rates it still glitches and holds. I'll overhaul it eventually...
  • I built a d-type flip-flop with an unconditional set and reset for the original shift register I used in the first version of my Turing machine model. It worked fine, but each flip-flop needed a pulse generator, two S&H nodes, and several expressions. Because of the pulse generator, the flip-flop wouldn’t clock at audio rates. I later replaced it with a simpler design without the pulse generator. I lost the unconditional reset, but gained simplicity and faster, more stable operation. As I’ve gained more experience with Audulus I’ve gotten a bit leery of pulse generating circuits. The timer works well at low frequencies but it does limit the maximum data rate.
  • @stschoen Gotcha, I seem to remember that now. This was the issue where everything looked correct but the due to audulus not having a separate signal path for dsp lead to things seizing up. I must confess as long as the reset input works reliably between 60bpm and 200bpm I am 100% AOK.
  • Here is a demo of how the timer-based counter can be used to loop bits of a 16-step sequence in a not totally random way. The top row of outputs on the sequencer sends a gate when the the step is active (just a copy of the clock signal) and the row of inputs below the knobs reset the sequence to that step.
    image

    The plan is to connect the pulse outs to earlier steps and create a shorter loop, but have that connection active only some of the time to create a recognizable over all pattern that is nonetheless non repeating.

    An accompanying melody is created by adding an sts uTuring machine output to this signal.
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  • @RobertSyrett, I agree, and I've kept the original shift register design for use in situations where high speed operation is less important than an async reset. I've also incorporated your timer-based reset circuit into the counters I'm using for the up-down arpeggiator and intend to retrofit the other models. I doubt anyone will find it necessary to clock the arpeggiator at 10K. (Hmmm, I wonder?)
  • Once again I'm back to dealing with reset issues. My recent Christmas Bells patch has a reset button which doesn't always work exactly right. The uSequencers I used had a reset that required a clock pulse to function which introduced some sync problems so I decided to do some further investigation. I concluded that almost all of my reset problems to date involve the inability to reset a sample and hold node so I fooled around until I came up with one that I think works. This involves a one frame delay so it wouldn't accept a high frequency signal on the reset line, but I can't imagine needing to do that. I did build one using a unit delay but I thought the extra CPU overhead wasn't necessary. Let me know if you're interested in the fast version. I also built a resettable flip-flop using the resettable S&H module. So far they seem to work pretty well. You can reset the S&H while the trigger is held high and it will output zero until both the reset and trigger go low. It reads the input on the leading edge of the next trigger.
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  • Cool! So this is the same idea as the reset I had made previously but with the absolute minimum delay rather than my best guess?
  • I think so. The unit delay version is probably faster, but I didn't think it was really necessary. The challenge was really figuring out how to get a one frame delay. The feedback delay node only delays when Audulus thinks it needs to insert it. I had to "trick" it into actually inserting the delay.
  • @stschoen - there's a one frame delay module in the new module collection - have you seen it?
  • Also you can force the unit delay to work wherever you want in a loop with the "Force Unit Delay" module i made under "building" - it's basically signal+(z-1[loop*0]) where signal is the beginning signal and loop is the point where you want to loop back from and have everything in between run at single sample speed.
  • @biminiroad, I looked but I couldn't find a one frame delay. The closest I could find was a one frame pulse. Maybe I overlooked it. Unlike the one frame pulse, it delays a gate by one frame but don't truncate it. In the case of the S&H I used it to delay the reset trigger until after the regular trigger was forced low. The unit delay version I built uses a similar approach to your "Force Unit Delay". I created a feedback loop from the output of the S&H to force the unit delay on. In this case, although it worked fine, I can't think of a situation where the increased speed would be useful. I did build a unit-delay based shift register that uses a "fast" flip-flop with no feedback loop for a module where I wanted to clock at audio rates. Because there is no one frame feedback delay in the flip-flop and only a one sample delay between each stage, the register will run at very high clock rates (>10k)
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