Summing Gates
  • So I was talking with my friend about how to sum gates together and have them retrigger as opposed to remain high and he suggested running the summed signal through a highpass filter (DCBlocker) to turn the gates into transients. That worked quite nicely! However, when I went to add some width back to the triggers, using a modified 1-shot envelope, I found that only some of the triggers were activating the envelope. Can anyone help with a diagnosis or workaround?
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  • i think the adder node is causing the problem cos it's method of Oring the two clocks gives you an output of 2 which you avert by divide by two... what i see when i slow down the clocks to observe what's happening is that the dcblock must be triggering on the second clock going off cos there is still a value of .5 above zero. slow down the clocks to see it dcblock creates a
    transient spike for the first clocks lo to hi transition, a second spike for the second clocks transition, lo to hi, then also for the second clocks hi to lo, ?because the first clock is still ON or hi or .5. due to 1/2....?? it gets a third false transient which is not what you want i think.
    can't get pic to paste ios bs
    can't dnload from ios

    u could process each clock thru seperate dcblockers independently which will get only transients at the leading edge of each clock,then into a divide by two expression, then into the adder ..then pulse stretcher.
  • Here's my solution! It involves using the WM controls to your advantage, plus a clamp(Gate,0,1) expression. If you use width modulation instead of trying to create pulses, you can control the way the note sustains. If you only use pulses, you're basically limited to ADR (instead of ADSR).

    Note: the demo patch is high CPU and may not run on all platforms.

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  • @biminiroad @hruffin3 Thank you for your replies. They were really helpful and I particularly enjoyed the composition you made, Mark! I probably should have been clearer about what I am doing and why I need to combine gates in the first place.

    I am going to a bay area modular meet-up where the event is to make a mega patch with everybody's portable set-ups, I have Audulus and an Intellijel Atlantis with an ES-8 and a few other things (https://www.modulargrid.net/e/racks/view/360884). As part of the conversation about using a master clock to control various elements different methods of summing gates came up and I was trying to get them to work in audulus so I could use them at the meet up. So I can't really anticipate the pulse width of the gates per se since they are coming from outside audulus.

    The problem with or gates and clamped sums is that they reduce the number of impulses, so rather than introducing complexity they add gaps.
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    I really liked the idea applying the applying the DCBlocker to the signal individually and then summing those, however it was still the case that not all of the transients were triggering the pulse-widening envelope.

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    So what I am thinking is that the scan rate of the inputs must be considerably lower than the sample rate of the transients being sent to it and some must be slipping through the cracks. This seems to hold true, because when I set the pulse width of a clock to .00001 and set the rate high, it created an inconsistent output on the waveform display.

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    I think I have found a workaround, using another method, but it is a limitation of Audulus that is good to be aware of. Hopefully as computers get faster this will not be an issue in the future.

    Wow, long post.

    TL:DR
    There is something fishy about the scan rate for inputs in Audulus so it doesn't always register very short transients.
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  • I see what you mean @RobertSyrett - Here's one way to do that with a little more reliability - you use a Delta module to detect when the summed value changes, and then you use a Flip-Flop to get the Delta to ignore one of the edges, then you just invert that and voila!

    And yeah, unless you have a z-1 single sample feedback loop, inputs are only being checked every ~300 frames (frame = 1 sample), so like every 0.0068 seconds for 44.1k sample rate.

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  • That is another useful technique, that I will probably use in future patches because the result is musical! However it has the following differences from the desired results:
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    It creates a gate signal when the gate drops as well as rises, and it rises from 0 to 1 and 1 to 2. So the flipflop ignores the second rise and picks up the second fall.

    Don't get me wrong, this actually is useful and worth using.
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  • @hruffin3 This video on might help out with uploading/downloading to the forum with iOS, unless you are using iPhone.
  • @robertsyrett - I see what you mean - however, if you keep the WM really low, it works pretty good for most things, especially if the clocks are at a rational ratio of time. I think we just need to build some kind of special "edge detector" and do something where it pulses whenever it sees a rising edge.
  • thought of this might as well try it seems to track betterimage
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